[SerialICE] New patch to review for serialice: 64f437a Add PCI bridge device filters
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Sun Oct 28 21:09:08 CET 2012
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1650
-gerrit
commit 64f437a78f1e65de6ba183516c869320f741c567
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Sun Oct 28 10:29:10 2012 +0200
Add PCI bridge device filters
Samples of decoding BARs as found on ich4, ihc7, i945 and i946
bridge devices. See board samples how to enable decoding.
Change-Id: I5b602ca51ac53cd6d61abed63450293fca2192f7
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
SerialICE/simba/i82801.lua | 159 +++++++++++++++++++++++++++++++++++++++++
SerialICE/simba/intel_bars.lua | 69 ++++++++++++++++++
SerialICE/simba/via_bars.lua | 30 ++++++++
3 files changed, 258 insertions(+)
diff --git a/SerialICE/simba/i82801.lua b/SerialICE/simba/i82801.lua
new file mode 100644
index 0000000..f06088d
--- /dev/null
+++ b/SerialICE/simba/i82801.lua
@@ -0,0 +1,159 @@
+-- **********************************************************
+--
+-- SMBus controller handling
+
+
+dofile("intel_smbus.lua")
+
+function smbus_bar_hook(f, action)
+ intel_smbus_setup(action.data, 0x20)
+end
+
+dev_sb_lpc = {
+ pci_dev = pci_bdf(0x0,0x1f,0x3,0x0),
+ name = "Smbus",
+ bar = {},
+}
+
+function enable_smbus_host_bar()
+ pci_cfg16_hook(dev_sb_lpc, 0x20, "SMBus", smbus_bar_hook)
+end
+
+
+-- **********************************************************
+--
+
+dev_power = {
+ pci_dev = pci_bdf(0x0,0x1f,0x0,0x0),
+ name = "SYS",
+ bar = {},
+ acpi = { f = nil },
+ tco = { f = nil },
+}
+
+function pm_io_bar(f, action)
+ f.dev.acpi.name = "ACPI"
+ f.dev.acpi.val = action.data
+ f.dev.acpi.size = 0x60
+ generic_io_bar(f.dev.acpi)
+
+ f.dev.tco.name = "TCO"
+ f.dev.tco.val = action.data + 0x60
+ f.dev.tco.size = 0x20
+ generic_io_bar(f.dev.tco)
+end
+
+function lpc_io_bar(f, action)
+ local base = bit32.band(action.data, 0xffff)
+ local mask = bit32.bor(bit32.rshift(action.data, 16), 3)
+ local size = mask + 1
+
+ base = bit32.band(base, bit32.bnot(mask))
+
+ add_bar(f.dev, f.reg, "LPC", size)
+ f.dev.bar[f.reg].val = base
+ generic_io_bar(f.dev.bar[f.reg])
+end
+
+function lpc_protect_serial_port(f, action)
+ drop_action(f, action, 0)
+end
+
+-- **********************************************************
+--
+-- AC '97 controller handling
+
+
+dev_audio = {
+ pci_dev = pci_bdf(0x0,0x1f,0x5,0x0),
+ name = "Audio",
+ bar = {}
+}
+
+function enable_audio_bars()
+ add_io_bar(dev_audio, 0x10, "NAMBAR", 0x100)
+ add_io_bar(dev_audio, 0x14, "NABMBAR", 0x40)
+ add_mem_bar(dev_audio, 0x18, "MMBAR", 0x200)
+ add_mem_bar(dev_audio, 0x1C, "MBBAR", 0x100)
+end
+
+dev_modem = {
+ pci_dev = pci_bdf(0x0,0x1f,0x6,0x0),
+ name = "Modem",
+ bar = {}
+}
+
+function enable_modem_bars()
+ add_io_bar(dev_modem, 0x10, "MMBAR", 0x100)
+ add_io_bar(dev_modem, 0x14, "MBAR", 0x80)
+end
+
+
+-- **********************************************************
+--
+-- i82801dx
+
+function enable_dx_power_bars()
+ pci_cfg16_hook(dev_power, 0x40, "PM", pm_io_bar)
+ add_io_bar(dev_power, 0x58, "GPIO", 0x40)
+end
+
+function enable_dx_lpc_bars()
+ pci_cfg8_hook(dev_power, 0xe0, "LPC", lpc_protect_serial_port)
+ pci_cfg8_hook(dev_power, 0xe6, "LPC", lpc_protect_serial_port)
+
+ add_io_bar(dev_power, 0xe4, "LPC1", 0x80)
+ add_io_bar(dev_power, 0xec, "LPC2", 0x10)
+end
+
+function enable_hook_i82801dx()
+ enable_smbus_host_bar()
+ enable_dx_power_bars()
+ enable_dx_lpc_bars()
+ enable_audio_bars()
+ enable_modem_bars()
+end
+
+-- **********************************************************
+--
+-- i82801gx
+
+-- ICH7 TPM
+-- Phoenix "Secure" Core bails out if we don't pass the read on ;-)
+filter_ich7_tpm = {
+ id = -1,
+ name = "ICH7 TPM",
+ pre = mem_target_only,
+ post = mem_base_post,
+ base = 0xfed40000,
+ size = 0x00001000,
+ hide = true
+}
+
+function enable_gx_power_bars()
+ pci_cfg16_hook(dev_power, 0x40, "PM", pm_io_bar)
+ add_io_bar(dev_power, 0x48, "GPIO", 0x40)
+end
+
+function enable_gx_lpc_bars()
+ pci_cfg8_hook(dev_power, 0x80, "LPC", lpc_protect_serial_port)
+ pci_cfg16_hook(dev_power, 0x82, "LPC", lpc_protect_serial_port)
+
+ pci_cfg32_hook(dev_power, 0x84, "LPC", lpc_io_bar)
+ pci_cfg32_hook(dev_power, 0x88, "LPC", lpc_io_bar)
+ pci_cfg32_hook(dev_power, 0x8c, "LPC", lpc_io_bar)
+ pci_cfg32_hook(dev_power, 0x90, "LPC", lpc_io_bar)
+end
+
+function enable_hook_i82801gx()
+ enable_hook(mem_hooks, filter_ich7_tpm)
+ add_mem_bar(dev_power, 0xf0, "RCBA", 0x4000)
+ enable_smbus_host_bar()
+ enable_gx_power_bars()
+ enable_gx_lpc_bars()
+ enable_audio_bars()
+ enable_modem_bars()
+end
+
+
+
diff --git a/SerialICE/simba/intel_bars.lua b/SerialICE/simba/intel_bars.lua
new file mode 100644
index 0000000..15607fd
--- /dev/null
+++ b/SerialICE/simba/intel_bars.lua
@@ -0,0 +1,69 @@
+
+-- **********************************************************
+-- Intel e7505
+
+dev_e7505_mch = {
+ pci_dev = pci_bdf(0x0,0x0,0x0,0x0),
+ name = "MCH",
+ bar = {}
+}
+
+function northbridge_e7505()
+ add_mem_bar(dev_e7505_mch, 0x14, "RCOMP", 0x1000)
+end
+
+-- **********************************************************
+-- Intel 82945 PCIe BAR
+
+function i945_pcie_bar(f, action)
+ local base = action.data
+ local sizebits = bit32.band(bit32.rshift(base, 1), 0x3)
+ local baseaddr = 0
+ local size = 0
+
+ if sizebits == 0 then
+ size = 256*1024*1024
+ baseaddr = bit32.band(base, 0xf0000000)
+ elseif sizebits == 1 then
+ size = 128*1024*1024
+ baseaddr = bit32.band(base, 0xf8000000)
+ elseif sizebits == 2 then
+ size = 64*1024*1024
+ baseaddr = bit32.band(base, 0xfc000000)
+ else
+ -- undefined, really
+ baseaddr = bit32.band(base, 0xfe000000)
+ size = 32*1024*1024
+ end
+
+ if bit32.band(base, 1) ~= 0 then
+ pcie_mm_enable(f.dev, f.reg, baseaddr, size)
+ else
+ pcie_mm_disable(f.dev, f.reg, baseaddr, size)
+ end
+end
+
+dev_i945 = {
+ pci_dev = pci_bdf(0,0,0,0),
+ name = "i945",
+ bar = {},
+}
+
+function northbridge_i945()
+ add_mem_bar(dev_i945, 0x40, "EPBAR", 4*1024)
+ add_mem_bar(dev_i945, 0x44, "MCHBAR", 16*1024)
+ add_mem_bar(dev_i945, 0x4c, "DMIBAR", 4*1024)
+ add_mem_bar(dev_i945, 0x60, "(unknown)", 4*1024)
+
+ pci_cfg32_hook(dev_i945, 0x48, "PCI", i945_pcie_bar)
+end
+
+function northbridge_i946()
+ add_mem_bar(dev_i945, 0x40, "PXPEPBAR", 4*1024)
+ add_mem_bar(dev_i945, 0x48, "MCHBAR", 16*1024)
+ add_mem_bar(dev_i945, 0x68, "DMIBAR", 4*1024)
+
+ pci_cfg32_hook(dev_i945, 0x60, "PCI", i945_pcie_bar)
+end
+
+
diff --git a/SerialICE/simba/via_bars.lua b/SerialICE/simba/via_bars.lua
new file mode 100644
index 0000000..7868535
--- /dev/null
+++ b/SerialICE/simba/via_bars.lua
@@ -0,0 +1,30 @@
+
+function sb_pcie_bar(dev, reg, base)
+ local baseaddr = bit32.lshift(base, 16)
+ local size = 64*1024
+
+ pcie_mm_cfg_bar(baseaddr, size)
+end
+
+dev_sb = {
+ pci_dev = pci_bdf(0,0x11,0,0),
+ name = "sb",
+ bar = {},
+}
+
+function nb_pcie_bar(dev, reg, base)
+ local size = 64*1024
+
+ pcie_mm_cfg_bar(base, size)
+end
+
+dev_nb = {
+ pci_dev = pci_bdf(0,0,0,0),
+ name = "nb",
+ bar = {},
+}
+
+function northbridge_vx900()
+ pci_cfg16_hook(dev_sb, 0xbd, "SB_PCI", sb_pcie_bar)
+ pci_cfg32_hook(dev_nb, 0x0, "NB_PCI", nb_pcie_bar)
+end
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