[SerialICE] Patch set updated for serialice: d51fc6f Reorganize code to support "high speed" serial transfers
Patrick Georgi (patrick@georgi-clan.de)
gerrit at coreboot.org
Sat Dec 3 20:32:45 CET 2011
Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/460
-gerrit
commit d51fc6feb10e755ad2b9d38502b3088d6167f240
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date: Thu Dec 1 12:09:56 2011 +0100
Reorganize code to support "high speed" serial transfers
This requires some chipset specific handling in case transfers
faster than 115200bps are used. Due to that, the build must be
reorganized a bit.
This change doesn't actually add high speed support code, but
does the reorganization only.
As an example, Kontron 986LCD-M was converted to "new-style":
southbridge code now resides in southbridge/intel-ich7.c,
superio code in superio/winbond-w83627thg.c, both pointed at
using Kconfig.
Other boards using this southbridge or superio can reuse the files,
reducing duplication.
Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
Change-Id: I5a36e939a15fea9ed58bf25dbcb322d0e6aa7c5a
---
SerialICE/Kconfig | 22 ++++++++
SerialICE/Makefile | 2 +-
SerialICE/chipset.c | 9 +++
SerialICE/mainboard/kontron_986lcd-m.c | 86 --------------------------------
SerialICE/serial.c | 10 ++++
SerialICE/serialice.c | 6 +-
SerialICE/southbridge/intel-ich7.c | 73 +++++++++++++++++++++++++++
SerialICE/superio/winbond-w83627thg.c | 58 +++++++++++++++++++++
8 files changed, 176 insertions(+), 90 deletions(-)
diff --git a/SerialICE/Kconfig b/SerialICE/Kconfig
index a28b4c5..48d43b7 100644
--- a/SerialICE/Kconfig
+++ b/SerialICE/Kconfig
@@ -124,6 +124,16 @@ config BOARD_INIT
default "hp_dl165_g6.c" if BOARD_HP_DL165_G6
default "wyse_s50.c" if BOARD_WYSE_S50
default "asrock_p4i65gv.c" if BOARD_ASROCK_P4I65GV
+
+config SOUTHBRIDGE_INIT
+ string
+ default "southbridge/intel-ich7.c" if BOARD_KONTRON_986LCD_M
+
+config SUPERIO_INIT
+ string
+ default "superio/winbond-w83627thg.c" if BOARD_KONTRON_986LCD_M
+
+
choice
prompt "Target communication"
@@ -192,6 +202,16 @@ choice
default SERIAL_115200
depends on SERIAL
+config SERIAL_460800
+ bool "460800 bps"
+ help
+ Set serial port speed to 460800 bps.
+
+config SERIAL_230400
+ bool "230400 bps"
+ help
+ Set serial port speed to 230400 bps.
+
config SERIAL_115200
bool "115200 bps"
help
@@ -221,6 +241,8 @@ endchoice
config SERIAL_BAUDRATE
int
+ default 460800 if SERIAL_460800
+ default 230400 if SERIAL_230400
default 115200 if SERIAL_115200
default 57600 if SERIAL_57600
default 38400 if SERIAL_38400
diff --git a/SerialICE/Makefile b/SerialICE/Makefile
index 2fce4cc..102be31 100644
--- a/SerialICE/Makefile
+++ b/SerialICE/Makefile
@@ -120,7 +120,7 @@ $(obj)/serialice.elf: $(obj)/serialice.o $(obj)/start.o $(src)/serialice.ld
$(obj)/serialice.S: $(SOURCES) $(obj)/romcc
$(Q)printf " ROMCC $(subst $(shell pwd)/,,$(@))\n"
- $(Q)$(obj)/romcc -mcpu=i386 $(INCLUDES) -I. -Imainboard -DVERSION=\"$(VERSION)\" -o $@.tmp $<
+ $(Q)$(obj)/romcc -mcpu=i386 $(INCLUDES) -I. -Imainboard -Isouthbridge -Isuperio -DVERSION=\"$(VERSION)\" -o $@.tmp $<
$(Q)printf ".section \".rom.text\"\n.globl main\nmain:\n" > $@
$(Q)cat $@.tmp >> $@
$(Q)rm $@.tmp
diff --git a/SerialICE/chipset.c b/SerialICE/chipset.c
index 97d0cbb..8ab4515 100644
--- a/SerialICE/chipset.c
+++ b/SerialICE/chipset.c
@@ -123,5 +123,14 @@ static void pnp_exit_ext_func_mode_ite(u16 port)
pnp_write_register(port, 0x02, 0x02);
}
+#ifndef CONFIG_SOUTHBRIDGE_INIT
+#define CONFIG_SOUTHBRIDGE_INIT "types.h"
+#endif
+#include CONFIG_SOUTHBRIDGE_INIT
+
+#ifndef CONFIG_SUPERIO_INIT
+#define CONFIG_SUPERIO_INIT "types.h"
+#endif
+#include CONFIG_SUPERIO_INIT
#include MAINBOARD
diff --git a/SerialICE/mainboard/kontron_986lcd-m.c b/SerialICE/mainboard/kontron_986lcd-m.c
index 53a7de0..62d8c46 100644
--- a/SerialICE/mainboard/kontron_986lcd-m.c
+++ b/SerialICE/mainboard/kontron_986lcd-m.c
@@ -21,92 +21,6 @@
const char boardname[33]="Kontron 986LCD-M ";
-/* Hardware specific functions */
-
-#define RCBA 0xfed1c000
-#define GCS 0x3410
-#define RCBA32(x) *((volatile u32 *)(RCBA + x))
-
-static void southbridge_init(void)
-{
- u16 reg16;
- u32 reg32;
-
- // Set up RCBA
- pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0xf0), RCBA | 1);
-
-#if 0
- // port80 writes go to LPC:
- reg32 = RCBA32(GCS);
- reg32 = reg32 & ~0x04;
- RCBA32(GCS) = reg32;
- outb(0x23, 0x80);
-#endif
-
- // Enable Serial IRQ
- pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0x64), 0xd0);
- // Set COM1/COM2 decode range
- pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0x80), 0x0010);
- // Enable COM1/COM2/KBD/SuperIO1+2
- pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0x82), 0x340b);
- // Enable HWM at 0xa00
- pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x84), 0x00fc0a01);
- // COM3 decode
- pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x88), 0x000403e9);
- // COM4 decode
- pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x8c), 0x000402e9);
- // io 0x300 decode
- pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x90), 0x00000301);
-
- // Disable watchdog
-#define PMBASE 0x500
-#define TCOBASE (PMBASE + 0x60)
- pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x40), PMBASE | 1);
- pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0x44), 0x80);
- reg16 = inw(TCOBASE + 0x08);
- reg16 |= (1 << 11);
- outw(reg16, TCOBASE + 0x08);
- outw(0x0008, TCOBASE + 0x04);
- outw(0x0002, TCOBASE + 0x06);
-}
-
-static void superio_init(void)
-{
- pnp_enter_ext_func_mode(0x2e);
-
- pnp_set_logical_device(0x2e, 2); // COM-A
- pnp_set_enable(0x2e, 0);
- pnp_set_iobase0(0x2e, 0x3f8);
- pnp_set_irq0(0x2e, 4);
- pnp_set_enable(0x2e, 1);
-
- pnp_set_logical_device(0x2e, 3); // COM-B
- pnp_set_enable(0x2e, 0);
- pnp_set_iobase0(0x2e, 0x2f8);
- pnp_set_irq0(0x2e, 3);
- pnp_set_enable(0x2e, 1);
-
- pnp_exit_ext_func_mode(0x2e);
-
- pnp_enter_ext_func_mode(0x4e);
-
- // Set COM3 to sane non-conflicting values
- pnp_set_logical_device(0x4e, 2); // COM-A
- pnp_set_enable(0x4e, 0);
- pnp_set_iobase0(0x4e, 0x3e8);
- pnp_set_irq0(0x4e, 11);
- pnp_set_enable(0x4e, 1);
-
- // Set COM4 to sane non-conflicting values
- pnp_set_logical_device(0x4e, 3); // COM-B
- pnp_set_enable(0x4e, 0);
- pnp_set_iobase0(0x4e, 0x2e8);
- pnp_set_irq0(0x4e, 10);
- pnp_set_enable(0x4e, 1);
-
- pnp_exit_ext_func_mode(0x4e);
-}
-
static void chipset_init(void)
{
southbridge_init();
diff --git a/SerialICE/serial.c b/SerialICE/serial.c
index 9aaecb6..eee7e49 100644
--- a/SerialICE/serial.c
+++ b/SerialICE/serial.c
@@ -39,7 +39,17 @@
static void sio_init(void)
{
+#if SIO_SPEED > 115200
+ /* "high speed" serial requires special chip setup
+ * (to be done in superio_init), and special divisor
+ * values (implement superio_serial_divisor() for that).
+ * Maybe it requires even more, but so far that seems
+ * to be enough.
+ */
+ int divisor = superio_serial_divisor(SIO_SPEED);
+#else
int divisor = 115200 / SIO_SPEED;
+#endif
int lcs = 3;
outb(0x00, SIO_PORT + UART_IER);
outb(0x01, SIO_PORT + UART_FCR);
diff --git a/SerialICE/serialice.c b/SerialICE/serialice.c
index 35531dc..649ee11 100644
--- a/SerialICE/serialice.c
+++ b/SerialICE/serialice.c
@@ -21,13 +21,13 @@
#include <serialice.h>
#include <io.h>
-/* SIO functions */
-#include "serial.c"
-
/* Hardware specific functions */
#include "chipset.c"
+/* SIO functions */
+#include "serial.c"
+
/* Accessor functions */
static void serialice_read_memory(void)
diff --git a/SerialICE/southbridge/intel-ich7.c b/SerialICE/southbridge/intel-ich7.c
new file mode 100644
index 0000000..3688084
--- /dev/null
+++ b/SerialICE/southbridge/intel-ich7.c
@@ -0,0 +1,73 @@
+/*
+ * SerialICE
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This initializes Intel's ICH7 that
+ * o the Super IO is accessible,
+ * o legacy serial port I/O ports are decoded,
+ * o the watchdog is turned off
+ */
+
+#define RCBA 0xfed1c000
+#define GCS 0x3410
+#define RCBA32(x) *((volatile u32 *)(RCBA + x))
+
+static void southbridge_init(void)
+{
+ u16 reg16;
+ u32 reg32;
+
+ // Set up RCBA
+ pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0xf0), RCBA | 1);
+
+#if 0
+ // port80 writes go to LPC:
+ reg32 = RCBA32(GCS);
+ reg32 = reg32 & ~0x04;
+ RCBA32(GCS) = reg32;
+ outb(0x23, 0x80);
+#endif
+
+ // Enable Serial IRQ
+ pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0x64), 0xd0);
+ // Set COM1/COM2 decode range
+ pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0x80), 0x0010);
+ // Enable COM1/COM2/KBD/SuperIO1+2
+ pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0x82), 0x340b);
+ // Enable HWM at 0xa00
+ pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x84), 0x00fc0a01);
+ // COM3 decode
+ pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x88), 0x000403e9);
+ // COM4 decode
+ pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x8c), 0x000402e9);
+ // io 0x300 decode
+ pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x90), 0x00000301);
+
+ // Disable watchdog
+#define PMBASE 0x500
+#define TCOBASE (PMBASE + 0x60)
+ pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x40), PMBASE | 1);
+ pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0x44), 0x80);
+ reg16 = inw(TCOBASE + 0x08);
+ reg16 |= (1 << 11);
+ outw(reg16, TCOBASE + 0x08);
+ outw(0x0008, TCOBASE + 0x04);
+ outw(0x0002, TCOBASE + 0x06);
+}
+
+
diff --git a/SerialICE/superio/winbond-w83627thg.c b/SerialICE/superio/winbond-w83627thg.c
new file mode 100644
index 0000000..5213921
--- /dev/null
+++ b/SerialICE/superio/winbond-w83627thg.c
@@ -0,0 +1,58 @@
+/*
+ * SerialICE
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This sets up the Super IO so up to 4 COM ports are usable */
+
+static void superio_init(void)
+{
+ pnp_enter_ext_func_mode(0x2e);
+
+ pnp_set_logical_device(0x2e, 2); // COM-A
+ pnp_set_enable(0x2e, 0);
+ pnp_set_iobase0(0x2e, 0x3f8);
+ pnp_set_irq0(0x2e, 4);
+ pnp_set_enable(0x2e, 1);
+
+ pnp_set_logical_device(0x2e, 3); // COM-B
+ pnp_set_enable(0x2e, 0);
+ pnp_set_iobase0(0x2e, 0x2f8);
+ pnp_set_irq0(0x2e, 3);
+ pnp_set_enable(0x2e, 1);
+
+ pnp_exit_ext_func_mode(0x2e);
+
+ pnp_enter_ext_func_mode(0x4e);
+
+ // Set COM3 to sane non-conflicting values
+ pnp_set_logical_device(0x4e, 2); // COM-A
+ pnp_set_enable(0x4e, 0);
+ pnp_set_iobase0(0x4e, 0x3e8);
+ pnp_set_irq0(0x4e, 11);
+ pnp_set_enable(0x4e, 1);
+
+ // Set COM4 to sane non-conflicting values
+ pnp_set_logical_device(0x4e, 3); // COM-B
+ pnp_set_enable(0x4e, 0);
+ pnp_set_iobase0(0x4e, 0x2e8);
+ pnp_set_irq0(0x4e, 10);
+ pnp_set_enable(0x4e, 1);
+
+ pnp_exit_ext_func_mode(0x4e);
+}
+
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